Building a 16-bit Processor Subset of LC-3 ISA
Generally, the processor will first fetch an instruction from the memory, decode it to determine the type of the instruction, execute the instruction as specified, and then fetch again repeating the process indefinitely.
The processor will first fetch an instruction from the memory by loading the current program counter (PC) into the memory address register (MAR). After loading this, it will wait for a cycle for the memory to be retrieved, and after waiting will load the memory data register (MDR) holding the instruction in memory at the specified address into the instruction register (IR). It then decodes the instruction to determine the operation that is requested. The 4 most significant bits (IR[15:12]) are encoded to represent different opcodes, which match up to various functions. For our specifications, we were asked to implement 9 different operations, including ADD, AND, NOT, LDR, STR, JSR, JMP, BR, and PSE.
After determining the operation requested, it will begin to step through the process for the given operation, enabling/disabling gates and muxes to guide the data from either memory or registers (specified by bits in the instruction) to wherever the data needs to go based on the operation type. For example, the ADD instruction will take data from a register and data from either a register or from bits in the instruction itself, and the processor will route the data from the register(s)/instruction to the ALU for computation, and then route the output of the ALU to wherever specified in the instruction (generally a register). During this computation, the processor also keeps track of condition codes (CC) which identify if an operation resulted in a positive, negative, or zero value; this can be used to create branching structures in code to create more complex and succinct code. After the operation finishes, the processor returns to the starting state and repeats the process of fetching and executing instructions over and over.